Rapid Prototyping of Field Programmable Gate Array-Based Discrete Cosine Transform Approximations

On the Implementation of a Wavelet-based Iterative Learning Controller Using CPLD/FPGA

The realization of a wavelet-based iterative learning controller (WILC) is presented in this paper. To meet the requirements of simplified hardware, fast rapid prototyping and fast up-date cycle, a wavelet-based iterative learning control system is implemented on a single FPGA (Field Programmable Gate Array) . There are three modules in this FPGA-based system, they are a feedback module, a disc...

Discrete Cosine Transform Algorithms for Fpga Devices

Building Blocks for MPEG Stream Processing

In the MPEG-1 multimedia standard, no encoding scheme is defined, but a generally accepted scheme includes the following building blocks: discrete cosine transform, quantization, zig-zag scanning, run-level coding, variable-length encoding, and motion estimation. In this paper, we describe the investigation into how such building blocks can be implemented in reconfigurable hardware, more specif...

Hardware Implementation of a Watermarking System for Mpeg

WATERMARKING SYSTEM FOR MPEG Mr.T.K (VLSI DESIGN, Anna University, Chennai, India,[email protected] ________________________________________________________________________________________________________ ABSTRACT-This project presents a hardware implementation of a digital watermarking system that can i information into compressed video streams in real time. The watermark embedding is p...

Scalable Architecture for Discrete Cosine Transform Computation Engine Based on Array Processors

We propose a scalable architecture for a Discrete Cosine Transform (DCT) computation engine based on Single Instruction stream and Multiple Data stream (SIMD) Array Processors. Each pixel of an input matrix is distributed across a 4-way connected Processing Element (PE); and a frame comprises several such PEs making it possible to compute as many pixels as the number of PEs in a frame. Tripling...